Daily reading: Signal VHDL explanation

Concept: delta delay

http://en.wikipedia.org/wiki/Delta_delay

Signal assignment and delta delay

Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:

signal_name <= value;  -- assigned after delta delay

http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.