Reason to initialize (not reset) signal in VHDL (Verilog)

http://stackoverflow.com/questions/6363130/is-there-a-reason-to-initialize-not-reset-signals-in-vhdl-and-verilog

signal, object declaration

Used to define an identifier as a signal object.
No explicit initialization of an object of type T causes the default
initialization at time zero to be the value of T'left

 signal identifier : subtype_indication [ signal_kind ] [ := expression ];

 signal a_bit : bit := '0';
 a_bit <= b_bit xor '1';    -- concurrent assignment

 signal my_word : word := X"01234567";
 my_word <= X"FFFFFFFF";           -- concurrent assignment

 signal foo : word register; -- guarded signal
 signal bar : word bus;      -- guarded signal
 signal join : word  wired_or; -- wired_or must be a resolution function

signal_kind may be register  or  bus.

A simple signal of an unresolved type can have only one driver.
Note that "bit" is an unresolved type as is "std_ulogic", but,
"std_logic" is a resolved type and allows multiple drivers of a
simple signal.

Initializing Signal

http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-18-initializing-signals.html