A TLB has a fixed number of slots that contain page table entries, which map virtual addresses to physical addresses. The virtual memory is the space seen from a process. This space is segmented in pages of a prefixed size. The page table
(generally loaded in memory) keeps track of where the virtual pages are
loaded in the physical memory. The TLB is a cache of the page table; that is, only a subset of its contents are stored.
The TLB references physical memory addresses in its table.
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