Showing posts with label Circuit. Show all posts
Showing posts with label Circuit. Show all posts

Saturday, April 20, 2013

Friday, March 29, 2013

Prototyping board soldering techniques


http://www.instructables.com/id/How-to-Prototype-Without-Using-Printed-Circuit-Boa/

Good practice for soldering
http://lbw.axe-man.org/solder/thumb.html

Progressive Prototyping techniques
http://elm-chan.org/docs/wire/wiring_e.html


http://electronics.stackexchange.com/questions/2215/how-do-i-connect-components-when-using-a-circuit-board-with-pads-but-no-traces

Monday, March 4, 2013

Daily reading: Signal VHDL explanation

Concept: delta delay

http://en.wikipedia.org/wiki/Delta_delay

Signal assignment and delta delay


Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:
signal_name <= value;  -- assigned after delta delay


http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.




Wednesday, February 27, 2013

AVR "lost bytes"

Stackexchange:


http://robotics.stackexchange.com/questions/99/how-to-manage-interrupts-on-an-avr

Wednesday, February 20, 2013

Tuesday, January 22, 2013

TMP 006 Breakout Board Build

Build
http://www.youtube.com/watch?v=8fXjTh1MMws
Test
http://www.youtube.com/watch?v=GEGiEi6tcVo&NR=1

TI Temperature Sensing Product line. 

Thursday, January 17, 2013

Signal Conditioning Piezoelectric Sensors

http://www.ti.com/lit/an/sloa033a/sloa033a.pdf

Mini Piezo Siren

http://www.rebelhosts.com/tt/te/p59.htm

Piezoelectric Tutorial From Physics to Ardurino
http://www.eng.utah.edu/~cs5968/handouts/piezo.pdf



Piezoelectric Amplifier Circuit

http://hackedgadgets.com/2009/05/06/piezoelectric-amplifier-circuit/

Sensing Amplifier Circuit


Transistor High Side Switching Interface

http://www.w9xt.com/page_microdesign_pt8_pnp_switching.html

Transistor Switching example
http://www.kpsec.freeuk.com/trancirc.htm

Transistor Tutorial

http://www.electronics-tutorials.ws/transistor/tran_1.html

How Piezo Buzzer works

http://www.engineersgarage.com/insight/how-piezo-buzzer-works?page=1


Saturday, December 29, 2012

Capacitor Discharging  Calculation

http://hyperphysics.phy-astr.gsu.edu/hbase/electric/capdis.html

1-Wire protocal
http://en.wikipedia.org/wiki/1-Wire

Sunday, November 18, 2012

Wired logic connection

http://en.wikipedia.org/wiki/Wired_logic_connection

Dailly Reading: Open collector

Applications of open-collector devices

Because the pull-up resistor is external and need not be connected to the chip supply voltage, a lower or higher voltage can be used instead.

Open collector circuits are therefore sometimes used to interface different families of devices that have different operating voltage levels. The open-collector transistor can be rated to withstand a higher voltage than the chip supply voltage. Such devices are commonly used to drive devices such as Nixie tubes, and vacuum fluorescent displays which require higher operating voltages than the usual 5-volt logic supply.

 
Another advantage is that more than one open-collector output can connect to a single line.

If all outputs attached to the line are in the high-impedance state, the pull-up resistor will hold the wire in a high voltage(logic 1) state.

 If one or more device outputs are in the logic 0 (ground) state, they will sink current and pull the line voltage toward ground.


 
Open-collector devices are commonly used to connect multiple devices to a bus (i.e., one carrying interrupt or write-enable signals). This enables one device to drive the bus without interference from the other inactive devices - if open-collector devices are not used, then the outputs of the inactive devices would attempt to hold the bus voltage high, resulting in unpredictable output.

By tying the output of several open collectors together, the common line becomes a "wired AND" (positive-true logic) or "wired OR" (negative-true logic) gate.

  A "wired OR" behaves like the boolean OR for negative-true logic, where the output is LOW if any one of its inputs is low. Such circuit constructions are termed "wired-AND" and "wired-OR", 

Hardware Porting Solution:

SCSI-1 devices use open collector for electrical signaling. [1] SCSI-2 and SCSI-3 may use EIA-485.

SCSI Parallel Interface??

Dailly reading: Tri-state logic and high impedence

Three-state logic
http://en.wikipedia.org/wiki/Three-state_logic

high impedance:
http://en.wikipedia.org/wiki/High_impedance

Digital electronics
High Impedance: Low current, high voltage
Low Impedance: Low voltage, High current


In digital circuits, a high impedance (also known as hi-Z, tri-stated or floating) output is not being driven to any defined logic level by the output circuit. The signal is neither driven to a logical high nor low level; this third condition lead to the description "tri-stated". Such a signal can be seen as an open circuit (or "floating" wire) because connecting it to a low impedance circuit will not affect that circuit; it will instead itself be pulled to the same voltage as the actively driven output. The combined input/output pins found on many ICs are actualy tri-state capable outputs which have been internally connected to inputs. This is the basis for bus-systems in computers, among many other uses.

The high-impedance state of a given node in a circuit cannot be verified by a voltage measurement alone. 

A pull-up resistor can be used to try to pull the wire to high and low voltage levels. If the nodes is not in a high-impedance state, extra current from the resistor will not significantly affect its voltage level.


Analog electronics:
The high impedance node is one that does not have any low impedance paths to any other nodes.

Three-state logic
3 state logic allows an output port to assume a high impedance state, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines.

Such as a bus which cannot listen to more than one device at a time.

Active low (OE output enable) which dictates whether the outputs should be held in high-impedance state or drive their respective loads (to either 0- or 1-level)


The whole concept of the third state is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logic 1)  against another device driving low (logical 0).

In particular, they are essential to the operation of a shared electronic bus.

Output enable vs. chip select

If CS is not asserted, the outputs are high impedance.
The difference lies in the time needed to output the signal. When chip select is deasserted, the chip does not operate internally, and there will be a significant delay between providing an address and receiving the data (An advantage of course, is that the chip consumes minimal power in this case.)

When chip select is asserted, the chip internally performs the access, and only the final output drivers are disabled by deasserting output enable. This can be done while the bus in use for other purposes.

Circuit designers will often use pull-up or pull-down resistors (usually within the range of 1-100kohm) to influence the circuit when the output is tri-stated. For example, I2C bus protocol (a bi-directional communication bus protocol often used between devices) specifies the use of pull-up resistors on the two communication lines. When devices are inactive, they "release " the communication lines and tri-state their outputs, thus removing their influence on the circuit. When all the devices on the bus have "released" the communication lines, the only influence on the circuit is the pull-up resistors, which pull the lines high. When a device wants to communicate, it comes out of the Hi-Z state and drives the line low. Devices communicating using this protocol either let the line float high, or drive it low-- thus preventing any bus contention situation where one device drives a line high and another low.


The PCI local bus provides pull-up resistors, but they would require several clock cycles to pull a signal high given the bus's large distributed capacitance. To enable high-speed operation, the protocol requires that every device connecting to the bus drive the important control signals high for at least one clock cycle before going to the Hi-Z state. This way, the pull-up resistors are only responsible for maintaining the bus signals in the face of leakage current.


Hardware configuration solution:
A three-state bus is typically used between chips on a single printed circuit board (PCB), or sometimes between PCBs plugged into a common backplane.
An open-collector bus is often used between PCBs plugged into a common backplane, or connected over longer cables.

Friday, June 22, 2012

Wiki Transimission Line

Wikipedia Transmission Line

http://en.wikipedia.org/wiki/Transmission_line

"However, when the voltage changes in a time interval comparable to the time it takes for the signal to travel down the wire, the length becomes important and the wire must be treated as a transmission line. Stated another way, the length of the wire is important when the signal includes frequency components with corresponding wavelengths comparable to or less than the length of the wire."

"A common rule of thumb is that the cable or wire should be treated as a transmission line if the length is greater than 1/10 of the wavelength. At this length the phase delay and the interference of any reflections on the line become important and can lead to unpredictable behavior in systems which have not been carefully designed using transmission line theory."