VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

http://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector

use ieee.numeric_std.all;
...
my_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length));

Multiple declaration of unsigned include via multiple use clauses; none are made directly visible

USE ieee.numeric_std.all;
USE ieee.std_logic_arith.ALL;

Reason to initialize (not reset) signal in VHDL (Verilog)

http://stackoverflow.com/questions/6363130/is-there-a-reason-to-initialize-not-reset-signals-in-vhdl-and-verilog

signal, object declaration

Used to define an identifier as a signal object.
No explicit initialization of an object of type T causes the default
initialization at time zero to be the value of T'left

 signal identifier : subtype_indication [ signal_kind ] [ := expression ];

 signal a_bit : bit := '0';
 a_bit <= b_bit xor '1';    -- concurrent assignment

 signal my_word : word := X"01234567";
 my_word <= X"FFFFFFFF";           -- concurrent assignment

 signal foo : word register; -- guarded signal
 signal bar : word bus;      -- guarded signal
 signal join : word  wired_or; -- wired_or must be a resolution function

signal_kind may be register  or  bus.

A simple signal of an unresolved type can have only one driver.
Note that "bit" is an unresolved type as is "std_ulogic", but,
"std_logic" is a resolved type and allows multiple drivers of a
simple signal.

Initializing Signal

http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-18-initializing-signals.html

Daily Reading: Difference between rising_edge(clk) and (clk'event and clk='1')

http://vhdlguru.blogspot.com/2010/04/difference-between-risingedgeclk-and.html

Unsigned Logic Vector Addition

http://stackoverflow.com/questions/5690750/unsigned-logic-vector-and-addition-how

In brief, you can add the ieee.numeric_std package to your architecture (library ieee; use ieee.numeric_std.all;) and then do the addition using:

Output <= std_logic_vector(unsigned(Output) + 1);

Daily reading: Signal VHDL explanation

Concept: delta delay

http://en.wikipedia.org/wiki/Delta_delay

Signal assignment and delta delay

Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:

signal_name <= value;  -- assigned after delta delay

http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.