VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

http://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector

use ieee.numeric_std.all;
...
my_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length));

Multiple declaration of unsigned include via multiple use clauses; none are made directly visible

USE ieee.numeric_std.all;
USE ieee.std_logic_arith.ALL;

Xilinx ISE VHDL to Symbol

http://www.xilinx.com/itp/xilinx10/isehelp/pp_p_process_create_schematic_symbol.htm

Schematic overview
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_schematic_overview.htm

Related discussion: Conversion of VHDL code to symbol
http://forums.xilinx.com/t5/Design-Entry/Conversion-of-VHDL-code-to-symbol/td-p/29535

ISE quick starting guide
http://cseweb.ucsd.edu/classes/wi11/cse141L/Media/Quick-Tutorial-11.pdf

Reason to initialize (not reset) signal in VHDL (Verilog)

http://stackoverflow.com/questions/6363130/is-there-a-reason-to-initialize-not-reset-signals-in-vhdl-and-verilog

signal, object declaration

Used to define an identifier as a signal object.
No explicit initialization of an object of type T causes the default
initialization at time zero to be the value of T'left

 signal identifier : subtype_indication [ signal_kind ] [ := expression ];

 signal a_bit : bit := '0';
 a_bit <= b_bit xor '1';    -- concurrent assignment

 signal my_word : word := X"01234567";
 my_word <= X"FFFFFFFF";           -- concurrent assignment

 signal foo : word register; -- guarded signal
 signal bar : word bus;      -- guarded signal
 signal join : word  wired_or; -- wired_or must be a resolution function

signal_kind may be register  or  bus.

A simple signal of an unresolved type can have only one driver.
Note that "bit" is an unresolved type as is "std_ulogic", but,
"std_logic" is a resolved type and allows multiple drivers of a
simple signal.

Initializing Signal

http://fpga-dsp-scratch.blogspot.com/2008/08/vhdl-part-18-initializing-signals.html

Daily Reading: Difference between rising_edge(clk) and (clk'event and clk='1')

http://vhdlguru.blogspot.com/2010/04/difference-between-risingedgeclk-and.html

FFT windowing Xilinx

http://tumblr.tristesse.org/post/3193756352/fft-windowing

Xilinx CoreGen Block Memory Generator

Memory Initialization:
http://cseweb.ucsd.edu/classes/sp08/cse141L/lab4/coregen-tutorial.html


Memory Initialization
http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v7_3/pg058-blk-mem-gen.pdf


The memory contents can be optionally initialized using a memory coefficient (COE) file or
by using the default data option. A COE file can define the initial contents of each individual
memory location, while the default data option defines the initial content of all locations.

Hints for creating COE files


How to open Memory Editor:
http://forums.xilinx.com/t5/Installation-and-Licensing/problem-in-memory-editor-in-ise-12-3/td-p/187608

Use Memory Editor:  

In ISE 10.1.03, Memory Editor can be accessed from the CORE Generator interface by selecting Tools -> Memory Editor.  

In ISE 11.1 and later, Memory Editor can be accessed from a script file. Use mem_edit.bat (Windows platforms) or mem_edit (Linux platforms). This script is available in the $XILINX/bin/&ltOS&gt directory. 

The Memory Editor can be used to create COE files in two ways: 

1. Enter your memory data values directly into the Memory Editor GUI and then select File -> Generate -> COE files(s) to create the COE files. 
2. Enter your memory data into Excel (use whatever formulas you need there), export to CSV format, and then Import the CSV into Memory Editor (File -> Import -> CSV file). When a CSV file is imported, Memory Editor prompts you to specify the Memory Depth, Word Width, Data and Address Radix, and Start Address. 

After the CSV file has been imported, you should inspect the Memory Content window for accuracy, and then select File -> Generate -> COE files(s) to create the COE files.


Creating a Memory
http://www.xilinx.com/itp/xilinx10/isehelp/cgn_p_memed_single_block.htm

Unsigned Logic Vector Addition

http://stackoverflow.com/questions/5690750/unsigned-logic-vector-and-addition-how

In brief, you can add the ieee.numeric_std package to your architecture (library ieee; use ieee.numeric_std.all;) and then do the addition using:

Output <= std_logic_vector(unsigned(Output) + 1);

Daily reading: Signal VHDL explanation

Concept: delta delay

http://en.wikipedia.org/wiki/Delta_delay

Signal assignment and delta delay

Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:

signal_name <= value;  -- assigned after delta delay

http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.

Wiki Transimission Line

Wikipedia Transmission Line

http://en.wikipedia.org/wiki/Transmission_line

"However, when the voltage changes in a time interval comparable to the time it takes for the signal to travel down the wire, the length becomes important and the wire must be treated as a transmission line. Stated another way, the length of the wire is important when the signal includes frequency components with corresponding wavelengths comparable to or less than the length of the wire."

"A common rule of thumb is that the cable or wire should be treated as a transmission line if the length is greater than 1/10 of the wavelength. At this length the phase delay and the interference of any reflections on the line become important and can lead to unpredictable behavior in systems which have not been carefully designed using transmission line theory."

What is stray capacitance?

What is stray capacitance?
http://www.edaboard.com/thread179679.html

Wiki
http://en.wikipedia.org/wiki/Capacitance#Stray_capacitance

sh can't open script? Quartus ii 11 + ubuntu 10.10

xx@xx-XXXXX:~/Quartus$ sh ./11.0sp1_quartus_free_linux.sh 
sh: Can't open ./11.0sp1_quartus_free_linux.sh


Solution:
http://ubuntuforums.org/showthread.php?t=1885162


bash ./11.0sp1_quartus_free_linux.sh


other problems report:
http://www.alteraforum.com/forum/showthread.php?t=31426


Installation guide:
http://fpga4u.epfl.ch/wiki/Install_Quartus_II#Download_the_Installer_2

Other installation problem:

./quartus: error while loading shared libraries: libsys_ictq.so: cannot open shared object file: No such file or directory

Cannot start the program:

Solution:

Repair broken link:

Add /opt/altera/version_number/quartus/linux(64)/

to ld.so.conf

Reference:
Lugman

Installation guide in PDF:
http://www.ece.auckland.ac.nz/~sinnen/QuartusII-on-UbuntuLinux.pdf

10.04 + Quartus 10
http://www.philpem.me.uk/elec/fpga/quartus-ubuntu/

Altera Wiki:
http://www.alterawiki.com/wiki/Quartus_for_Linux

Installation Manual from Altera official
http://www.altera.com/literature/manual/quartus_install.pdf


Right path to run program:

quartus/bin
http://alterauserforums.net/forum/showthread.php?p=117571

Make sure PATH point to quartus/bin

Install USB-Blaster Driver:

Please reference
Writing udev rules
http://www.reactivated.net/writing_udev_rules.html#syntax

Altera provides little support for the USB-Blaster drivers, only Red Hat is officially supported. Depending on your Linux distribution you will have to work a little to make it work. We will progressively add in the following subsections the information to install the USB-Blaster for each distribution. It will be difficult for us to test every distribution of Linux, so if your distribution is not listed there but one of the solution worked or if you had to look for a solution elsewhere, we encourage you to contribute to these subsections by sharing your experience.

To let users use the USB-Blaster device, you need to give them the right to. On Gentoo, you must add your user to the usb group (in /etc/group) to be able to program the device. On other distributions, you need to have write access to /proc/bus/usb/bus/id.

Here is an example for Ubuntu:

• Create a new rule file with your favorite text editor (like vim):

sudo vim /etc/udev/rules.d/51-usbblaster.rules

• Insert the following lines

# Altera USB-Blaster rule to set mode to 666.
SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c"

• Load this new rule by typing:

sudo udevadm control --reload-rules

http://blog.codingwell.net/2011/03/quartus-programmer-linux.html


solve permission problem

We need to patch the JTAG server to look for devices in /sys/kernel/debug/usb/devices instead of /proc/bus/usb/devices, and in /dev/bus/usb/.../.../ instead of /proc/bus/usb/.../.../.

As the former won't fit in the string placeholder of the binary file, we choose to create a soft link.

sudo ln -s /sys/kernel/debug/usb/devices /dev/bus/usb/devices

This soft link will disappear on reboot, so if you don't want to type it every time, add this line in a script or in your /etc/rc.local file (without the sudo).

Now we will use sed to replace the paths that the JTAG server is looking at. There are 2 sets of commands, one for 32-bit OS and the other one for 64-bit. Select the set corresponding to your system. If you have a doubt, it won't harm to patch both files. Before executing the commands, replace<installation path> by your installation path (e.g., /opt/altera/10.0). Note that these commands will create a backup copy of the JTAG server (jtagd.bak).

For 32-bit OS:

sudo sed -i.bak 's/\/proc\/bus\/usb\/%03u\/%03u/\/dev\/bus\/usb\/%03u\/%03u\d0/g' <installation path>/quartus/linux/jtagd
sudo sed -i 's/\/proc\/bus\/usb\/devices/\/dev\/bus\/usb\/devices\d0/g' <installation path>/quartus/linux/jtag

sed
Search and Replace

Discussion on how to set up usb-blaster under ubuntu
http://www.alteraforum.com/forum/showthread.php?t=5893&page=7

USB configuration under debian:
http://www.eecg.toronto.edu/~laforest/USB-Blaster-Debian.html