Exploring the /proc/net Directory
http://www.onlamp.com/pub/a/linux/2000/11/16/LinuxAdmin.html
more can be found in linux man page:
http://linux.die.net/man/5/proc
Showing posts with label Computer Architecture. Show all posts
Showing posts with label Computer Architecture. Show all posts
Wednesday, May 8, 2013
Monday, March 4, 2013
Daily reading: Signal VHDL explanation
Concept: delta delay
http://en.wikipedia.org/wiki/Delta_delay
Signal assignment and delta delay
Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:
http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.
http://en.wikipedia.org/wiki/Delta_delay
Signal assignment and delta delay
- signal_name <= value; -- assigned after delta delay
http://www.pldworld.net/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm
When no explicit delay time is provided, the default time is a delay called delta delay.
Tuesday, February 26, 2013
Nested Interrupt ARM Example
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11008.html
Friday, December 7, 2012
Sunday, October 28, 2012
Cache Mapping
Cache to Ram Ration
A processor might have 512 KB of Cache and 512 MB of RAM.
There may be 1000 times more RAM than cache.
The cache algorithms have to carefully select the 0.1% of the memory that is likely to be most accessed.
A cache line contains two fields
Data from RAM
The address of the block is called the tag field.
Mapping:
The memory system has to quickly determine if a given address is in the cache.
Three popular methods of mapping addresses to cache locations.
-- Fully Associative
Search the entire cache for an address.
--Direct
Each address has a specific place in the cache.
--Set Associative
Each address can be in any of a small set of cache locations.
Searching Problem
Knowledge of searching
Linear Search O(n)
Binary Search O(log2 (n))
Hashing O(1)
Parallel Search O(n/p)
Associative Mapping
The data from any location in RAM can be stored in any location in cache.
When the processor wants an address, all tag fields in the cache as checked to determine if the data is already in the cache.
Each tag line requires circuitry to compare the desired address with the tag field.
All tag fields are checked in parallel.
Set Associative Mapping
Set associative mapping is a mixture of direct and associative mapping.
The cache lines are grouped into sets.
Replacement policy
When a cache miss occurs, data is copied into some location in cache.
With Set Associative of Fully Associative mapping, the system must decide where to put the data and what values will be replaced.
Cache performance is greatly affected by properly choosing data that is unlikely to referenced again.
Replacement Options
First In First Out (FIFO)
Least Recently Used (LRU)
Pseudo LRU
Random
Comparison of Mapping Fully Associatve
Associate mapping works the best, but is complex to implement. Each tag line requires circuitry to compare the desired address with the tag field.
Some special purpose $, such as the virtual memory Translation Lookaside Buffer (TLB) is an associative cache.
Comparison of Mapping Direct.
Has the lowest performance, but is easiest to implement. Direct is often used for instruction cache.
Sequential addresses fill a cache line and then go to the next cache line.
A processor might have 512 KB of Cache and 512 MB of RAM.
There may be 1000 times more RAM than cache.
The cache algorithms have to carefully select the 0.1% of the memory that is likely to be most accessed.
A cache line contains two fields
Data from RAM
The address of the block is called the tag field.
Mapping:
The memory system has to quickly determine if a given address is in the cache.
Three popular methods of mapping addresses to cache locations.
-- Fully Associative
Search the entire cache for an address.
--Direct
Each address has a specific place in the cache.
--Set Associative
Each address can be in any of a small set of cache locations.
Searching Problem
Knowledge of searching
Linear Search O(n)
Binary Search O(log2 (n))
Hashing O(1)
Parallel Search O(n/p)
Associative Mapping
The data from any location in RAM can be stored in any location in cache.
When the processor wants an address, all tag fields in the cache as checked to determine if the data is already in the cache.
Each tag line requires circuitry to compare the desired address with the tag field.
All tag fields are checked in parallel.
Set Associative Mapping
Set associative mapping is a mixture of direct and associative mapping.
The cache lines are grouped into sets.
Replacement policy
When a cache miss occurs, data is copied into some location in cache.
With Set Associative of Fully Associative mapping, the system must decide where to put the data and what values will be replaced.
Cache performance is greatly affected by properly choosing data that is unlikely to referenced again.
Replacement Options
First In First Out (FIFO)
Least Recently Used (LRU)
Pseudo LRU
Random
Comparison of Mapping Fully Associatve
Associate mapping works the best, but is complex to implement. Each tag line requires circuitry to compare the desired address with the tag field.
Some special purpose $, such as the virtual memory Translation Lookaside Buffer (TLB) is an associative cache.
Comparison of Mapping Direct.
Has the lowest performance, but is easiest to implement. Direct is often used for instruction cache.
Sequential addresses fill a cache line and then go to the next cache line.
Interleaving & Memory Interleaving
Computer Memory, Communication system, error correction,
http://en.wikipedia.org/wiki/Interleaving
http://fourier.eng.hmc.edu/e85/lectures/memory/node2.html
http://en.wikipedia.org/wiki/Interleaving
http://fourier.eng.hmc.edu/e85/lectures/memory/node2.html
Issues Related to Cache Memory
- Load-ThroughWhen the CPU needs to read a word from the memory, the block containing the word is brought from MM to CM, while at the same time the word is forwarded to the CPU.
- Store-ThroughIf store-through is used, a word to be stored from CPU to memory is written to both CM (if the word is in there) and MM. By doing so, a CM block to be replaced can be overwritten by an in-coming block without being saved to MM.
CUDA Shared Memory broadcast
Multiple addresses map to same memory bank
Accesses are serialized
Hardware splits request into as many separate conflict-free requests as necessary
Exception: if all access the same address: broadcast
However, recent large improvements in CUBLAS and CUFFT performance were achieved by avoiding shared memory in favor of registers -- so try to use registers whenever possible.
If all threads read from the same shared memory address then a broadcast mechanism is automatically invoked and serialization is avoided. Shared memory broadcasts are an excellent and high-performance way to get data to many threads simultaneously.
It is worthwhile trying to exploit this feature whenever you use shared memory.
----Rob Farber
www.drdobbs.com/parallel/cuda-supercomputing-for-the-masses-part/208801731
CUDA, Supercomputing for the masses: Part 5
Accesses are serialized
Hardware splits request into as many separate conflict-free requests as necessary
Exception: if all access the same address: broadcast
However, recent large improvements in CUBLAS and CUFFT performance were achieved by avoiding shared memory in favor of registers -- so try to use registers whenever possible.
If all threads read from the same shared memory address then a broadcast mechanism is automatically invoked and serialization is avoided. Shared memory broadcasts are an excellent and high-performance way to get data to many threads simultaneously.
It is worthwhile trying to exploit this feature whenever you use shared memory.
----Rob Farber
www.drdobbs.com/parallel/cuda-supercomputing-for-the-masses-part/208801731
CUDA, Supercomputing for the masses: Part 5
Monday, October 15, 2012
Today's reading: Computer Architecture: Appendix B1
Reviews of Memory Hierarchy
Palt When the processor references an item within a page that is not present in cache or main memory.
Palt occurs.
Palt When the processor references an item within a page that is not present in cache or main memory.
Palt occurs.
Sunday, October 14, 2012
Inside Nehalem: Intel’s Future Processor and System
http://www.realworldtech.com/nehalem/7/
L1D Cache?
Inclusive caches are forced by design to replicate data, which implies certain relationships between the sizes of the various levels of the cache. In the case of Nehalem, each core contains 64KB of data in the L1 caches and 256KB in the L2 cache (there may or may not be data that is in both the L1 and L2 caches).
This means that 1-1.25MB of the 8MB L3 cache in Nehalem is filled with data that is also in other caches. What this means is that inclusive caches should only really be used where there is a fairly substantial size difference between the two levels. Nehalem has about an 8X difference between the sum of the four L2 caches and the L3, while Barcelona’s L3 cache is the same size as the total of the L2 caches.
Nehalem’s cache hierarchy has also been made more flexible by increasing support for unaligned accesses.
As a result, an unaligned SSE load or store will always have the same latency as an aligned memory access, so there is no particular reason to use aligned SSE memory accesses.
L1D Cache?
Inclusive caches are forced by design to replicate data, which implies certain relationships between the sizes of the various levels of the cache. In the case of Nehalem, each core contains 64KB of data in the L1 caches and 256KB in the L2 cache (there may or may not be data that is in both the L1 and L2 caches).
This means that 1-1.25MB of the 8MB L3 cache in Nehalem is filled with data that is also in other caches. What this means is that inclusive caches should only really be used where there is a fairly substantial size difference between the two levels. Nehalem has about an 8X difference between the sum of the four L2 caches and the L3, while Barcelona’s L3 cache is the same size as the total of the L2 caches.
Nehalem’s cache hierarchy has also been made more flexible by increasing support for unaligned accesses.
As a result, an unaligned SSE load or store will always have the same latency as an aligned memory access, so there is no particular reason to use aligned SSE memory accesses.
Saturday, October 13, 2012
TLB Translation Lookaside Buffer
A TLB has a fixed number of slots that contain page table entries, which map virtual addresses to physical addresses. The virtual memory is the space seen from a process. This space is segmented in pages of a prefixed size. The page table
(generally loaded in memory) keeps track of where the virtual pages are
loaded in the physical memory. The TLB is a cache of the page table; that is, only a subset of its contents are stored.
The TLB references physical memory addresses in its table.
The TLB references physical memory addresses in its table.
Saturday, April 28, 2012
Daily Reading: Locality of reference
Spatial Locality, Temporal Locality, relevant knowledge of cache. (wiki)
http://en.wikipedia.org/wiki/Locality_of_reference#Use_of_spatial_and_temporal_locality:_hierarchical_memory
http://en.wikipedia.org/wiki/Locality_of_reference#Use_of_spatial_and_temporal_locality:_hierarchical_memory
Texture memory speed test
Speed test program
http://forums.nvidia.com/index.php?showtopic=181432&st=0
"On Fermi, global memory loads are cached in L1 and L1 cache has higher bandwidth than the texture cache"
http://stackoverflow.com/questions/9893086/why-in-my-case-the-texture-memory-is-slower-than-the-global
Spatial Locality of texture memory usage.
http://forums.nvidia.com/index.php?showtopic=181432&st=0
"On Fermi, global memory loads are cached in L1 and L1 cache has higher bandwidth than the texture cache"
http://stackoverflow.com/questions/9893086/why-in-my-case-the-texture-memory-is-slower-than-the-global
Spatial Locality of texture memory usage.
Cache & Cache miss or hit
Most modern desktop and server CPUs have at least three independent caches: an Instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, and a translation lookaside buffer (TLB)???? used to speed up virtual-to-physical address translation for both executable instruction and data.
Cache Entries
Memory is split into "locations," which correspond to cache "lines".
The requested memory location (now called a tag)
a copy of the data
When the processor needs to read or write a location in main memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain in that address. If the processor finds that the memory location is in the cache, a cache hit has occurred (otherwise, a cache miss).
A cache miss refers to a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency.
Three kinds of cache misses : instruction read miss, data read miss, and data write miss.
A cache read miss from an instruction cache generally causes the most delay, because the processor, or at least the thread of execution, has to wait (stall) until the instruction is fetched from main memory.
A cache read miss from a data cache usually causes less delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution.
A cache write miss to a data cache generally causes the least delay, because the write can be queued and there are few limitations on the execution of subsequent instructions. The processor can continue until the queue is full.
Reference:
http://en.wikipedia.org/wiki/CPU_cache#Cache_miss
Cache Entries
Memory is split into "locations," which correspond to cache "lines".
The requested memory location (now called a tag)
a copy of the data
When the processor needs to read or write a location in main memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain in that address. If the processor finds that the memory location is in the cache, a cache hit has occurred (otherwise, a cache miss).
A cache miss refers to a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency.
Three kinds of cache misses : instruction read miss, data read miss, and data write miss.
A cache read miss from an instruction cache generally causes the most delay, because the processor, or at least the thread of execution, has to wait (stall) until the instruction is fetched from main memory.
A cache read miss from a data cache usually causes less delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution.
A cache write miss to a data cache generally causes the least delay, because the write can be queued and there are few limitations on the execution of subsequent instructions. The processor can continue until the queue is full.
Reference:
http://en.wikipedia.org/wiki/CPU_cache#Cache_miss
Friday, April 27, 2012
Translation lookaside buffer (wiki)
A translation lookaside buffer (TLB) is a cache that memory management hardware uses to improve virtual address translation speed. All current desktop, notebook, and server processors use a TLB to map virtual and physical address spaces, and it is nearly always present in any hardware which utilizes virtual memory.
Reference:Wiki
Reference:Wiki
Friday, March 30, 2012
Tuesday, February 14, 2012
Several Concepts: Locality of references
http://en.wikipedia.org/wiki/Locality_of_reference
Use locality in general and matrix multiplication example.
Use locality in general and matrix multiplication example.
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